Static Timing Analysis

Project : CF_audio
Build Time : 01/15/16 16:04:58
Device : CY8C3866LTI-030
Temperature : -40C - 85/125C
VDDA : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VDDOPAMP : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Setup
CyBUS_CLK CyBUS_CLK -9.611
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 66.000 MHz 66.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 66.000 MHz 66.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 66.000 MHz 66.000 MHz 40.383 MHz Frequency
CyPLL_OUT CyPLL_OUT 66.000 MHz 66.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 15.1515ns(66 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
LRC(0)_SYNC/out \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 40.383 MHz 24.763 -9.611 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 LRC(0)_SYNC LRC(0)_SYNC/clock LRC(0)_SYNC/out 1.480
Route 1 Net_409_SYNCOUT LRC(0)_SYNC/out \ShiftReg_1:bSR:status_0\/main_1 4.234
macrocell3 U(0,5) 1 \ShiftReg_1:bSR:status_0\ \ShiftReg_1:bSR:status_0\/main_1 \ShiftReg_1:bSR:status_0\/q 3.350
Route 1 \ShiftReg_1:bSR:status_0\ \ShiftReg_1:bSR:status_0\/q \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 4.729
datapathcell2 U(0,4) 1 \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\ SETUP 10.970
Clock Skew 0.000
LRC(0)_SYNC/out \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 40.773 MHz 24.526 -9.374 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 LRC(0)_SYNC LRC(0)_SYNC/clock LRC(0)_SYNC/out 1.480
Route 1 Net_409_SYNCOUT LRC(0)_SYNC/out \ShiftReg_2:bSR:status_0\/main_1 4.238
macrocell4 U(1,5) 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/main_1 \ShiftReg_2:bSR:status_0\/q 3.350
Route 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/q \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 4.488
datapathcell4 U(1,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\ SETUP 10.970
Clock Skew 0.000
LRC(0)_SYNC/out \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\/cs_addr_1 41.315 MHz 24.204 -9.052 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 LRC(0)_SYNC LRC(0)_SYNC/clock LRC(0)_SYNC/out 1.480
Route 1 Net_409_SYNCOUT LRC(0)_SYNC/out \ShiftReg_1:bSR:status_0\/main_1 4.234
macrocell3 U(0,5) 1 \ShiftReg_1:bSR:status_0\ \ShiftReg_1:bSR:status_0\/main_1 \ShiftReg_1:bSR:status_0\/q 3.350
Route 1 \ShiftReg_1:bSR:status_0\ \ShiftReg_1:bSR:status_0\/q \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\/cs_addr_1 4.170
datapathcell1 U(1,4) 1 \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\ SETUP 10.970
Clock Skew 0.000
LRC(0)_SYNC/out \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/cs_addr_1 42.477 MHz 23.542 -8.390 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 LRC(0)_SYNC LRC(0)_SYNC/clock LRC(0)_SYNC/out 1.480
Route 1 Net_409_SYNCOUT LRC(0)_SYNC/out \ShiftReg_2:bSR:status_0\/main_1 4.238
macrocell4 U(1,5) 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/main_1 \ShiftReg_2:bSR:status_0\/q 3.350
Route 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/q \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/cs_addr_1 3.504
datapathcell3 U(0,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\ SETUP 10.970
Clock Skew 0.000
\ShiftReg_1:bSR:load_reg\/q \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 44.244 MHz 22.602 -7.450 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,5) 1 \ShiftReg_1:bSR:load_reg\ \ShiftReg_1:bSR:load_reg\/clock_0 \ShiftReg_1:bSR:load_reg\/q 1.250
Route 1 \ShiftReg_1:bSR:load_reg\ \ShiftReg_1:bSR:load_reg\/q \ShiftReg_1:bSR:status_0\/main_0 2.303
macrocell3 U(0,5) 1 \ShiftReg_1:bSR:status_0\ \ShiftReg_1:bSR:status_0\/main_0 \ShiftReg_1:bSR:status_0\/q 3.350
Route 1 \ShiftReg_1:bSR:status_0\ \ShiftReg_1:bSR:status_0\/q \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 4.729
datapathcell2 U(0,4) 1 \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\ SETUP 10.970
Clock Skew 0.000
\ShiftReg_2:bSR:load_reg\/q \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 44.733 MHz 22.355 -7.203 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,5) 1 \ShiftReg_2:bSR:load_reg\ \ShiftReg_2:bSR:load_reg\/clock_0 \ShiftReg_2:bSR:load_reg\/q 1.250
Route 1 \ShiftReg_2:bSR:load_reg\ \ShiftReg_2:bSR:load_reg\/q \ShiftReg_2:bSR:status_0\/main_0 2.297
macrocell4 U(1,5) 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/main_0 \ShiftReg_2:bSR:status_0\/q 3.350
Route 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/q \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 4.488
datapathcell4 U(1,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\ SETUP 10.970
Clock Skew 0.000
\ShiftReg_1:bSR:load_reg\/q \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\/cs_addr_1 45.366 MHz 22.043 -6.891 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,5) 1 \ShiftReg_1:bSR:load_reg\ \ShiftReg_1:bSR:load_reg\/clock_0 \ShiftReg_1:bSR:load_reg\/q 1.250
Route 1 \ShiftReg_1:bSR:load_reg\ \ShiftReg_1:bSR:load_reg\/q \ShiftReg_1:bSR:status_0\/main_0 2.303
macrocell3 U(0,5) 1 \ShiftReg_1:bSR:status_0\ \ShiftReg_1:bSR:status_0\/main_0 \ShiftReg_1:bSR:status_0\/q 3.350
Route 1 \ShiftReg_1:bSR:status_0\ \ShiftReg_1:bSR:status_0\/q \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\/cs_addr_1 4.170
datapathcell1 U(1,4) 1 \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\ SETUP 10.970
Clock Skew 0.000
\ShiftReg_2:bSR:load_reg\/q \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/cs_addr_1 46.792 MHz 21.371 -6.219 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,5) 1 \ShiftReg_2:bSR:load_reg\ \ShiftReg_2:bSR:load_reg\/clock_0 \ShiftReg_2:bSR:load_reg\/q 1.250
Route 1 \ShiftReg_2:bSR:load_reg\ \ShiftReg_2:bSR:load_reg\/q \ShiftReg_2:bSR:status_0\/main_0 2.297
macrocell4 U(1,5) 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/main_0 \ShiftReg_2:bSR:status_0\/q 3.350
Route 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/q \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/cs_addr_1 3.504
datapathcell3 U(0,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\ SETUP 10.970
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_5 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/cs_addr_0 49.261 MHz 20.300 -5.148 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_137 \Control_Reg_1:Sync:ctrl_reg\/control_5 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/cs_addr_0 6.750
datapathcell4 U(1,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\ SETUP 10.970
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_5 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/cs_addr_0 50.620 MHz 19.755 -4.603 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_137 \Control_Reg_1:Sync:ctrl_reg\/control_5 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/cs_addr_0 6.205
datapathcell3 U(0,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\ SETUP 10.970
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\ShiftReg_1:bSR:sC16:BShiftRegDp:u0\/sol_msb \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\/sir 1.240
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,4) 1 \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\ \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\/clock \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\/sol_msb 1.240
Route 1 \ShiftReg_1:bSR:sC16:BShiftRegDp:u0.sol_msb__sig\ \ShiftReg_1:bSR:sC16:BShiftRegDp:u0\/sol_msb \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\/sir 0.000
datapathcell2 U(0,4) 1 \ShiftReg_1:bSR:sC16:BShiftRegDp:u1\ HOLD 0.000
Clock Skew 0.000
\ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/sol_msb \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/sir 1.240
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\ \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/clock \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/sol_msb 1.240
Route 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0.sol_msb__sig\ \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/sol_msb \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/sir 0.000
datapathcell4 U(1,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\ HOLD 0.000
Clock Skew 0.000
Net_410__SYNC/out \ShiftReg_1:bSR:load_reg\/clk_en 2.316
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,5) 1 Net_410__SYNC Net_410__SYNC/clock Net_410__SYNC/out 0.000
Route 1 Net_410__SYNC_OUT Net_410__SYNC/out \ShiftReg_1:bSR:load_reg\/clk_en 2.316
macrocell6 U(0,5) 1 \ShiftReg_1:bSR:load_reg\ HOLD 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_5 \ShiftReg_1:bSR:StsReg\/status_2 2.677
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_5 2.040
Route 1 Net_137 \Control_Reg_1:Sync:ctrl_reg\/control_5 \ShiftReg_1:bSR:StsReg\/status_2 2.637
statusicell1 U(0,3) 1 \ShiftReg_1:bSR:StsReg\ HOLD -2.000
Clock Skew 0.000
Net_410__SYNC_1/out \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/clk_en 2.770
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,5) 1 Net_410__SYNC_1 Net_410__SYNC_1/clock Net_410__SYNC_1/out 0.000
Route 1 Net_410__SYNC_OUT_1 Net_410__SYNC_1/out \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/clk_en 2.770
datapathcell4 U(1,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\ HOLD 0.000
Clock Skew 0.000
Net_410__SYNC_1/out \ShiftReg_2:bSR:load_reg\/clk_en 2.770
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,5) 1 Net_410__SYNC_1 Net_410__SYNC_1/clock Net_410__SYNC_1/out 0.000
Route 1 Net_410__SYNC_OUT_1 Net_410__SYNC_1/out \ShiftReg_2:bSR:load_reg\/clk_en 2.770
macrocell7 U(1,5) 1 \ShiftReg_2:bSR:load_reg\ HOLD 0.000
Clock Skew 0.000
Net_410__SYNC_1/out \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/clk_en 2.794
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,5) 1 Net_410__SYNC_1 Net_410__SYNC_1/clock Net_410__SYNC_1/out 0.000
Route 1 Net_410__SYNC_OUT_1 Net_410__SYNC_1/out \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/clk_en 2.794
datapathcell3 U(0,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\ HOLD 0.000
Clock Skew 0.000
Net_410__SYNC_1/out \ShiftReg_2:bSR:SyncCtl:CtrlReg\/clk_en 3.665
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,5) 1 Net_410__SYNC_1 Net_410__SYNC_1/clock Net_410__SYNC_1/out 0.000
Route 1 Net_410__SYNC_OUT_1 Net_410__SYNC_1/out \ShiftReg_2:bSR:SyncCtl:CtrlReg\/clk_en 3.665
controlcell3 U(1,4) 1 \ShiftReg_2:bSR:SyncCtl:CtrlReg\ HOLD 0.000
Clock Skew 0.000
Net_410__SYNC_1/out \ShiftReg_2:bSR:StsReg\/clk_en 3.665
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,5) 1 Net_410__SYNC_1 Net_410__SYNC_1/clock Net_410__SYNC_1/out 0.000
Route 1 Net_410__SYNC_OUT_1 Net_410__SYNC_1/out \ShiftReg_2:bSR:StsReg\/clk_en 3.665
statusicell2 U(1,4) 1 \ShiftReg_2:bSR:StsReg\ HOLD 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_5 \ShiftReg_2:bSR:StsReg\/status_2 3.759
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_5 2.040
Route 1 Net_137 \Control_Reg_1:Sync:ctrl_reg\/control_5 \ShiftReg_2:bSR:StsReg\/status_2 3.719
statusicell2 U(1,4) 1 \ShiftReg_2:bSR:StsReg\ HOLD -2.000
Clock Skew 0.000
+ Input To Output Section
Source Destination Delay (ns)
AF_IN(0)_PAD AF_OUT(0)_PAD 39.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
CF_audio 1 AF_IN(0)_PAD AF_IN(0)_PAD AF_IN(0)_PAD 0.000
Route 1 AF_IN(0)_PAD AF_IN(0)_PAD AF_IN(0)/pad_in 0.000
iocell41 P1[7] 1 AF_IN(0) AF_IN(0)/pad_in AF_IN(0)/fb 6.881
Route 1 Net_375 AF_IN(0)/fb Net_371/main_2 5.984
macrocell2 U(0,3) 1 Net_371 Net_371/main_2 Net_371/q 3.350
Route 1 Net_371 Net_371/q AF_OUT(0)/pin_input 5.538
iocell40 P15[7] 1 AF_OUT(0) AF_OUT(0)/pin_input AF_OUT(0)/pad_out 17.994
Route 1 AF_OUT(0)_PAD AF_OUT(0)/pad_out AF_OUT(0)_PAD 0.000
+ Input To Clock Section
+ CyBUS_CLK
Source Destination Delay (ns)
AF_IN(0)_PAD \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/route_si 27.165
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 AF_IN(0)_PAD AF_IN(0)_PAD AF_IN(0)/pad_in 0.000
iocell41 P1[7] 1 AF_IN(0) AF_IN(0)/pad_in AF_IN(0)/fb 6.881
Route 1 Net_375 AF_IN(0)/fb Net_303/main_1 5.984
macrocell1 U(0,3) 1 Net_303 Net_303/main_1 Net_303/q 3.350
Route 1 Net_303 Net_303/q \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\/route_si 4.170
datapathcell3 U(0,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u0\ SETUP 6.780
Clock Clock path delay 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
LRC(0)_SYNC/out AF_OUT(0)_PAD 55.009
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 LRC(0)_SYNC LRC(0)_SYNC/clock LRC(0)_SYNC/out 1.480
Route 1 Net_409_SYNCOUT LRC(0)_SYNC/out \ShiftReg_2:bSR:status_0\/main_1 4.238
macrocell4 U(1,5) 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/main_1 \ShiftReg_2:bSR:status_0\/q 3.350
Route 1 \ShiftReg_2:bSR:status_0\ \ShiftReg_2:bSR:status_0\/q \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 4.488
datapathcell4 U(1,5) 1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\ \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/cs_addr_1 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/so_comb 10.890
Route 1 Net_416 \ShiftReg_2:bSR:sC16:BShiftRegDp:u1\/so_comb Net_371/main_3 3.681
macrocell2 U(0,3) 1 Net_371 Net_371/main_3 Net_371/q 3.350
Route 1 Net_371 Net_371/q AF_OUT(0)/pin_input 5.538
iocell40 P15[7] 1 AF_OUT(0) AF_OUT(0)/pin_input AF_OUT(0)/pad_out 17.994
Route 1 AF_OUT(0)_PAD AF_OUT(0)/pad_out AF_OUT(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_5 CF_CS(0)_PAD 26.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_137 \Control_Reg_1:Sync:ctrl_reg\/control_5 CF_CS(0)/pin_input 8.078
iocell35 P12[7] 1 CF_CS(0) CF_CS(0)/pin_input CF_CS(0)/pad_out 16.263
Route 1 CF_CS(0)_PAD CF_CS(0)/pad_out CF_CS(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_1 REC_LED(0)_PAD 26.671
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_132 \Control_Reg_1:Sync:ctrl_reg\/control_1 REC_LED(0)/pin_input 8.061
iocell30 P15[3] 1 REC_LED(0) REC_LED(0)/pin_input REC_LED(0)/pad_out 16.030
Route 1 REC_LED(0)_PAD REC_LED(0)/pad_out REC_LED(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 PLAY_LED(0)_PAD 26.073
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_135 \Control_Reg_1:Sync:ctrl_reg\/control_0 PLAY_LED(0)/pin_input 5.469
iocell29 P15[6] 1 PLAY_LED(0) PLAY_LED(0)/pin_input PLAY_LED(0)/pad_out 18.024
Route 1 PLAY_LED(0)_PAD PLAY_LED(0)/pad_out PLAY_LED(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_4 CF_RESET(0)_PAD 25.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_4 2.580
Route 1 Net_136 \Control_Reg_1:Sync:ctrl_reg\/control_4 CF_RESET(0)/pin_input 7.310
iocell32 P15[5] 1 CF_RESET(0) CF_RESET(0)/pin_input CF_RESET(0)/pad_out 15.807
Route 1 CF_RESET(0)_PAD CF_RESET(0)/pad_out CF_RESET(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_6 EXEC_LED(0)_PAD 24.433
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_6 2.580
Route 1 Net_138 \Control_Reg_1:Sync:ctrl_reg\/control_6 EXEC_LED(0)/pin_input 6.707
iocell43 P12[4] 1 EXEC_LED(0) EXEC_LED(0)/pin_input EXEC_LED(0)/pad_out 15.146
Route 1 EXEC_LED(0)_PAD EXEC_LED(0)/pad_out EXEC_LED(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_3 CF_REG(0)_PAD 23.899
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_134 \Control_Reg_1:Sync:ctrl_reg\/control_3 CF_REG(0)/pin_input 6.008
iocell33 P15[4] 1 CF_REG(0) CF_REG(0)/pin_input CF_REG(0)/pad_out 15.311
Route 1 CF_REG(0)_PAD CF_REG(0)/pad_out CF_REG(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK(fixed-function)
Source Destination Delay (ns)
\I2C_1:I2C_FF\/sda_out SDA_1(0)_PAD:out 25.071
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_1:I2C_FF\ \I2C_1:I2C_FF\/clock \I2C_1:I2C_FF\/sda_out 1.000
Route 1 \I2C_1:Net_643_1\ \I2C_1:I2C_FF\/sda_out SDA_1(0)/pin_input 7.818
iocell8 P12[1] 1 SDA_1(0) SDA_1(0)/pin_input SDA_1(0)/pad_out 16.253
Route 1 SDA_1(0)_PAD SDA_1(0)/pad_out SDA_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C_1:I2C_FF\/scl_out SCL_1(0)_PAD:out 24.548
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_1:I2C_FF\ \I2C_1:I2C_FF\/clock \I2C_1:I2C_FF\/scl_out 1.000
Route 1 \I2C_1:Net_643_0\ \I2C_1:I2C_FF\/scl_out SCL_1(0)/pin_input 8.664
iocell9 P12[0] 1 SCL_1(0) SCL_1(0)/pin_input SCL_1(0)/pad_out 14.884
Route 1 SCL_1(0)_PAD SCL_1(0)/pad_out SCL_1(0)_PAD:out 0.000
Clock Clock path delay 0.000